FEATURES
Arm Cortex-M3 CPU, operating at up to 120 MHz (LPC1768/67/66/65/64/63) or up to 100 MHz (LPC1768/67/66/65/64/63) (LPC1769). There is a Memory Protection Unit (MPU) with support for eight regions.
Built-in Nested Vectored Interrupt Controller for the Arm Cortex-M3 (NVIC).
On-chip flash programming memory of up to 512 kB. A better flash memory accelerator enables 120 MHz operating at high speed with no wait states.
Using the on-chip bootloader software, in-system programming (ISP) and in-application programming (IAP) are possible.
On the AHB multilayer matrix, there is an eight channel General Purpose DMA controller (GPDMA) that may be used for memory-to-memory transfers as well as SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals.
Internal RC oscillator running at 4 MHz with optional system clock functionality and accuracy cut to 1%.
PLL eliminates the requirement for a high-frequency crystal and enables CPU operation at the maximum CPU rate. can be powered by the RTC oscillator, internal RC oscillator, or main oscillator.
For more versatility, use USB PLL.
Code Read Protection (CRP) with several degrees of security
Serial number specific to the gadget for identification.
APPLICATION
eMetering
alarm mechanisms
the lighting
white products
Business networking
motor management
The ARM Cortex-M3 based LPC1769/68/67/66/65/64/63 microcontrollers for embedded applications have a high degree of integration and consume little power. Next-generation cores like the Arm Cortex-M3 provide system improvements including improved debug tools and deeper support block integration.
The CPU frequencies used by the LPC1768/67/66/65/64/63 are up to 100 MHz. Up to 120 MHz of CPU frequency are supported by the LPC1769. The Arm Cortex-M3 CPU employs a Harvard architecture with a three-stage pipeline, distinct local instruction and data buses, and a third bus for peripherals. Additionally, the inbuilt prefetch unit of the Arm Cortex-M3 CPU allows speculative branching.
The LPC1769/68/67/66/65/64/63's peripheral complement consists of up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 8- Pin compatibility exists between the 100-pin LPC236x Arm7-based microcontroller family and the LPC1769/68/67/66/65/64/63
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