SPECIFICATIONS - PIC18F4620 I/P - Microchip

• C compiler optimized RISC architecture
• Internal oscillator support-31KHz to 8MHz with 4xPLL
• A fail-safe clock monitor allows a safe shutdown if the clock fails
• Watchdog timer with separate RC oscillator
• An integrated LCD driver module, capable of driving 48 segments and 4 commons for LCD display
• 10-bit ADC, 12 channels, and 100K samples per second
• The programmable low voltage detection module
• Programmable brown-out-reset module
• EUSART module including LIN bus support
• Run, idle, and sleep modes
• Idle mode currents down to 5.8µA typical
• Sleep mode currents down to 0.1µA typical
• Supplier's original packaging: Tube

FEATURES - PIC18F4620 I/P - Microchip

• Employing crystal or ceramic resonators, four crystal modes
•  Two external clock modes allow for the use of either one pin (oscillator input with the other pin reassigned as general I/O) or two pins (oscillator input plus a divide-by-4 clock output).
•  Two additional RC oscillator modes share the same pin configurations as external clock modes.
• An internal oscillator block that offers a total of 8 clock frequencies, 6 user-selectable clock frequencies between 125 kHz and 4 MHz, an INTRC source (about 31 kHz), and an 8 MHz clock. The two oscillator pins are made available for further general-purpose use with this option. I/O
• A Phase Lock Loop (PLL) frequency multiplier may be used with the Internal Oscillator and High-Speed Crystal modes to increase clock speeds up to 40 MHz. Without the need for an external crystal or clock circuit, the PLL provides users with a full range of clock rates, from 31 kHz to 32 MHz, when used with the internal oscillator.The internal oscillator block offers a steady reference source in addition to serving as a clock source, giving the family additional capabilities for reliable operation:
• Fail-Safe Clock Monitor: Using an internal oscillator as a reference signal, this option continuously checks the primary clock source. The controller switches to the internal oscillator block in the event of a clock breakdown, enabling safe application shutdown or ongoing low-speed operation.
• Two-Speed Start-up: Until the principal clock source is available, this option enables the inner oscillator to act as the master clock from Power-on Reset or wake the device from the Sleep state.