Features

Core

• A 3-stage pipeline and a 16 MHz advanced STM8 core with Harvard design.

• Comprehensive instruction set

Memories

• Flash memory 8 Kbytes for programme memory; data retention after 100 cycles at 55 °C: 20 years.

RAM: 1 kilobyte.

• Data memory: genuine data EEPROM with 128 bytes that can withstand 100k write/erase cycles.

converter from analog to digital (ADC)

• 10-bit ADC, 1 LSB ADC, scan mode, and analogue watchdog; ADC with up to 5 multiplexed channels;

I/Os

• A 32-pin package with up to 28 I/Os, including 21 high-sink outputs

• Extremely durable I/O architecture that resists current injection